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UPSD325X датащи(PDF) 166 Page - STMicroelectronics |
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UPSD325X датащи(HTML) 166 Page - STMicroelectronics |
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166 / 176 page ![]() µPSD325X DEVICES 166/176 Figure 85. Reset (RESET) Timing Table 135. Reset (RESET) Timing (5V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 136. Reset (RESET) Timing (3V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 137. VSTBYON Definitions Timing (5V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Table 138. VSTBYON Timing (3V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Symbol Parameter Conditions Min Max Unit tNLNH RESET Active Low Time 1 150 ns tNLNH–PO Power-on Reset Active Low Time 1 ms tNLNH–A Warm RESET 2 25 µs tOPR RESET High to Operational Device 120 ns Symbol Parameter Conditions Min Max Unit tNLNH RESET Active Low Time 1 300 ns tNLNH–PO Power-on Reset Active Low Time 1 ms tNLNH–A Warm RESET 2 25 µs tOPR RESET High to Operational Device 300 ns Symbol Parameter Conditions Min Typ Max Unit tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs tBXBL VSTBY Off Detection to VSTBYON Output Low (Note 1) 20 µs Symbol Parameter Conditions Min Typ Max Unit tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs tBXBL VSTBY Off Detection to VSTBYON Output Low (Note 1) 20 µs tNLNH-PO tOPR AI02866b RESET tNLNH tNLNH-A tOPR VCC V CC(min) Power-On Reset Warm Reset |
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