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UPSD325X датащи(PDF) 122 Page - STMicroelectronics

номер детали UPSD325X
подробное описание детали  Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
PDF  176 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD325X датащи(HTML) 122 Page - STMicroelectronics

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µPSD325X DEVICES
122/176
Decode PLD (DPLD)
The DPLD, shown in Figure 59, is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
s
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
s
4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
s
1 internal SRAM Select (RS0) signal (two
product terms)
s
1 internal CSIOP Select signal (selects the PSD
MODULE registers)
s
2 internal Peripheral Select signals (Peripheral
I/O Mode).
Figure 59. DPLD Logic Array
Note: 1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I /O PORTS (PORT A,B,C)1
(8)
PGR0 - PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]2
(2)
(4)
PD[2:1]
PSEN, RD, WR, ALE2
(1)
(1)
RESET
2
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
AI06601
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1



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