PIC16F15213 datasheet(101/439 Pages) MICROCHIP

101 / 439 page

13.

Sleep Mode

13.1

Sleep Mode Operation

Sleep mode is entered by executing the SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for

operation during Sleep.

The PD bit is cleared.

The TO bit is set.

The CPU and the System clocks are disabled.

LFINTOSC and/or HFINTOSC will remain enabled if any peripheral has requested them as a clock source or if

the HFOEN, MFOEN or LFOEN bits are set.

ADC is unaffected if the ADCRC oscillator is selected. When the ADC clock is something other than ADCRC,

a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although

the ADON bit remains active.

I/O ports maintain the status they had before SLEEP was executed (driving high, low, or high-impedance) only

if no peripheral connected to the I/O port is active.

Refer to individual sections for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions need to be considered:

• I/O pins will not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using any oscillator

I/O pins that are high-impedance inputs need to be pulled to VDD or VSS externally to avoid switching currents caused

by floating inputs.

13.1.1

Wake-Up from Sleep

The device can wake up from Sleep through one of the following events:

External Reset input on MCLR pin, if enabled.

BOR Reset, if enabled.

POR Reset.

Watchdog Timer, if enabled.

Any external interrupt.

Interrupts by peripherals capable of running during Sleep (see the individual peripheral for more information).

The first three events will cause a device Reset. The last three events are considered a continuation of program

execution. To determine whether a device Reset or wake-up event occurred, refer to the “Determining the Cause of

a Reset” section in the “Resets” chapter.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake up

through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of

the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP

instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction and will then call

the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the

user needs to have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

PIC16F15213/14/23/24/43/44

Sleep Mode

and its subsidiaries

Data Sheet

DS40002195E-page 101

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