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KSZ9567RTXI-TR датащи(PDF) 119 Page - Microchip Technology |
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KSZ9567RTXI-TR датащи(HTML) 119 Page - Microchip Technology |
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119 / 232 page ![]() 2017-2019 Microchip Technology Inc. DS00002329D-page 119 KSZ9567R 5.1.6.16 GPIO Status Monitor 1 Register This register provides the interrupt status for the trigger output unit and timestamp units used with the GPIO. The GPIO pin Output Trigger and Timestamp Unit interrupt status bit in the Global Interrupt Status Register is the OR of the status bits in this register. 2:0 Event Trigger Output Unit Done (TRIGGER_DONE) (Bit 2 = Trigger Unit 2, Bit 1 = Trigger Unit 1, Bit 0 = Trigger Unit 0) 1 = The event trigger output unit has been generated when the TRIG- GER_NOTIFY bit is set to “1” in the Trigger Output Unit Control 1 Register (write “1” to clear this bit) and will generate an interrupt to the host. 0 = Event trigger output unit not done. R/W1C 000b Address: 0x0528 - 0x052B Size: 32 bits Bits Description Type Default 31:19 RESERVED RO 0x0000 18:16 Trigger Output Unit Interrupt Status (Bit 18 = Trigger Unit 2, Bit 17 = Trigger Unit 1, Bit 16 = Trigger Unit 0) These three bits provide the interrupt status for the three Trigger Output Units. These interrupts are enabled by setting the TRIGGER_NOTIFY bit in the Trigger Output Unit Control 1 Register. This is done separately for each TOU. Refer to the GPIO Status Monitor 0 Register for the Trigger Output Unit status details. 1 = Interrupt detected 0 = No interrupt R/WC 000b 15:2 RESERVED RO 0x0000 1:0 Timestamp Unit Interrupt Status (GPIO input timestamp only) (Bit 1 = Timestamp Unit 1, Bit 0 = Timestamp Unit 0) These two bits provide the interrupt status for the two Timestamp Output Units for the GPIO. These interrupts are enabled by the Timestamp Unit Interrupt Enable bit in the Timestamp Control and Status Register. This is done separately for each TSU. Refer to the registers beginning at the Timestamp Status and Control Register for Timestamp interrupt details. For the interrupt status for the port-based timestamping of PTP egress frames, refer to the Port Interrupt Status Register and Port PTP Timestamp Interrupt Status Register. 1 = Interrupt detected 0 = No interrupt R/WC 00b Bits Description Type Default |
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