ST25R3916 datasheet(156/157 Pages) STMICROELECTRONICS

156 / 157 page

Revision history

ST25R3916/7

156/157

DS12484 Rev 4

04-Jun-2020

Updated Features, Section 2: Description, Section 2.2.13: RX decoding,

Section 2.2.14: FIFO and Section 7: Ordering information,

Updated Table 6: First and third zero setting, Table 27: ISO14443A and

NFC 106kb/s settings register, Table 33: Stream mode definition register,

Table 81: Passive target modulated and unmodulated state driver output

resistance, Table 85: Resistive AM modulated state driver output

resistance, Table 119: Operating conditions and Table 133: 3.4 MHz AC

characteristics.

Added footnote 2 to Table 36: Auxiliary definition register.

Added Figure 32: RPmin vs. VDD, fc = 3.4 MHz and Figure 33: Maximum

Rbus value vs. bus parasitic capacitance, fc = 3.4 MHz.

Minor text edits across the whole document.

06-Aug-2021

Updated Section 2: Description.

Updated Figure 1: Minimum system configuration - Single sided antenna

driving, Figure 2: Minimum system configuration - Differential antenna

driving, Figure 20: Writing a single register, Figure 21: Writing register

data with auto-incrementing address and Figure 22: Reading a single

byte from a register.

Updated Table 2: ST25R3916 - VFQFPN32 and WLCSP36 pin

assignment, Table 12: I2C interface and interrupt signal lines, Table 78:

RFO driver resistance, Table 118: Absolute maximum ratings, Table 119:

Operating conditions, footnote 1 of Table 120: Characteristics of CMOS

I/Os, footnote 13 of Table 121: ST25R3916/7 electrical characteristics

(VDD = 3.3 V), Table 122: ST25R3916/7 electrical characteristics (VDD =

5.5 V) and its footnote 8.

Added footnotes to tables 78, 81, 85, 121, 122 and 123.

Minor text edits across the whole document.

Table 136. Document revision history (continued)

Date

Revision

Changes

ST25R3916 датащи(PDF) 156 Page - STMicroelectronics