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8.4.3.2 MCU_NAVSS0

MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated

in the MCU domain.

MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator

(UDMASS), and Peripherals (Module subsystem [MODSS]).

UDMASS – UDMASS is the essential part of the DMA Architecture. UDMASS consists of:

• Unified DMA Controller

• Ring Accelerator

• Packet Streaming Interface (PSILSS)

MODSS – MODSS is a collection of peripherals with different system-level functions. NAVSS0 contains the

following modules:

• Memory CRC module

• Infrastructure components such as CBASS, proxies, interrupt aggregators, and an interrupt router

ECC aggregators – for SEC/DED memory protection.

For more information, see Navigator Subsystem (NAVSS) section in the device TRM.

8.4.4 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs

of peripherals, which perform data transfers using memory mapped registers (MMRs) accessed via a standard

non-coherent bus fabric. The PDMA module is located close to one or more peripherals which require an

external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting

only statically configured Transfer Request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the peripherals

themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data

stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of

the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to

a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.

For more information, see PDMA Controller section in the device TRM.

www.ti.com

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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