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AM6546 датащи(PDF) 244 Page - Texas Instruments

номер детали AM6546
подробное описание детали  AM654x, AM652x Sitara™ Processors Silicon Revision 2.1
PDF  284 Pages
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домашняя страница  http://www.ti.com
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AM6546 датащи(HTML) 244 Page - Texas Instruments

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7.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
PMIT5
td(TX_CLK-TXD)
Delay time, TX_CLK High to TXD[3:0] valid
10 Mbps
0
25
ns
td(TX_CLK-TX_EN)
Delay time, TX_CLK to TX_EN valid
0
25
ns
td(TX_CLK-TXD)
Delay time, TX_CLK High to TXD[3:0] valid
100
Mbps
0
25
ns
td(TX_CLK-TX_EN)
Delay time, TX_CLK to TX_EN valid
0
25
ns
PMIT5
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
SPRS91x_TIMING_PRU_MII_RT_07
Figure 7-121. PRU_ICSSG MII_TXD[3:0], MII_TXEN Timing
For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem - Gigabit (PRU_ICSSG) in the device TRM.
7.9.5.22 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Section 7.9.5.22.1, Section 7.9.5.22.2 and Figure 7-122 present timings and switching characteristics of the
Timers.
7.9.5.22.1 Timing Requirements for Timers
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T1
tw(TINPH)
Pulse duration, high
CAPTURE
5 + 4P(1)
ns
T2
tw(TINPL)
Pulse duration, low
CAPTURE
5 + 4P(1)
ns
(1)
P = functional clock period in ns.
7.9.5.22.2 Switching Characteristics for Timers
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
tw(TOUTH)
Pulse duration, high
PWM
-3 + 4P(1)
ns
T4
tw(TOUTL)
Pulse duration, low
PWM
-3 + 4P(1)
ns
(1)
P = functional clock period in ns.
T1
T2
TIMIx
TIMER_01
T3
T4
TIMOx
Figure 7-122. Timer Timing
For more information, see section Timers in the device TRM.
AM6548, AM6528, AM6546, AM6526
SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021
www.ti.com
244
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