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Table 7-69. OSPI Timing Requirements - DDR Mode

see Figure 7-89

NO.

MODE

MIN

MAX

UNIT

O15 tsu(D-LBCLK)

Setup time, D[i:0](1) valid before active LBCLK

(DQS) edge

1.8V, External Board Loopback

0.52

3.3V, External Board Loopback

1.97

O16 th(LBCLK-D)

Hold time, D[i:0](1) valid after active LBCLK (DQS)

edge

1.8V, External Board Loopback

1.24 (2)

3.3V, External Board Loopback

1.44 (2)

O17 tsu(D-DQS)

Setup time, D[i:0](1) valid before active DQS edge

1.8V, DQS

-0.46

3.3V, DQS

-0.66

O18 th(DQS-D)

Hold time, D[i:0](1) valid after active DQS edge

1.8V, DQS

3.59

3.3V, DQS

8.89

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the

SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to Section 9.2.2 for more

details.

OSPI_DQS

OSPI_D[i:0]

O16

O15

OSPI_TIMING_04

Figure 7-89. OSPI Timing Requirements - DDR, External Loopback Clock and DQS

7.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode

NO. PARAMETER DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

tw(CLKL)

Pulse duration, CLK low

-0.3+0.475×P

(2)

tw(CLKH)

Pulse duration, CLK high

-0.3+0.475×P

(2)

td(CLK-CSn)

Delay time, CSn active edge to CLK rising edge

1.8 V

0.475 × P +

0.975 × N × R

(2) (3) (5)

0.475 × P +

0.975 × N × R

+ 7.7 (2) (3) (5)

3.3 V

0.475 × P +

0.975 × N × R

(2) (3) (5)

0.475 × P +

0.975 × N × R

+ 8 (2) (3) (5)

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8 V

0.475 × P +

0.975 × N × R

- 7.7(2) (4) (5)

0.475 × P +

0.975 × N × R

(2) (4) (5)

3.3 V

0.475 × P +

0.975 × N × R

- 8(2) (4) (5)

0.475 × P +

0.975 × N × R

(2) (4) (5)

td(CLK-D)

Delay time, CLK active edge to D[i:0](1)

transition

1.8 V

-7.7

-1.56

3.3 V

-7.7

-1.56

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

P = CLK cycle time = SCLK period

(3)

N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5)

R = refclk

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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