CC2430-RTR1-F32 datasheet(169/234 Pages) TI

169 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 169 of 232

RFIM (0x91) – RF Interrupt Mask

Bit

Name

Reset

R/W

Description

Voltage regulator for radio has been turned on

Interrupt disabled

IM_RREG_PD

R/W

Interrupt enabled

TX completed with packet sent

Interrupt disabled

IM_TXDONE

R/W

Interrupt enabled

Number of bytes in RXFIFO is above threshold set by

IOCFG0.FIFOP_THR

Interrupt disabled

IM_FIFOP

R/W

Interrupt enabled

Start of frame delimiter (SFD) has been detected

Interrupt disabled

IM_SFD

R/W

Interrupt enabled

Clear channel assessment (CCA) indicates that channel is clear

Interrupt disabled

IM_CCA

R/W

Interrupt enabled

CSMA-CA/strobe processor (CSP) wait condition is true

Interrupt disabled

IM_CSP_WT

R/W

Interrupt enabled

CSMA-CA/strobe processor (CSP) program execution stopped

Interrupt disabled

IM_CSP_STOP

R/W

Interrupt enabled

CSMA-CA/strobe processor (CSP) INT instruction executed

Interrupt disabled

IM_CSP_INT

R/W

Interrupt enabled

14.5 FIFO access

The TXFIFO and RXFIFO may be

accessed through the SFR register RFD

(0xD9).

Data is written to the TXFIFO when writing

to the RFD register. Data is read from the

he RXFIFO when the RFD register is read.

The RF register bits RFSTATUS.FIFO and

RFSTATUS.FIFOP provide information on

the data in the receive FIFO, as described

in section 14.6 on page 170. Note that the

RFSTATUS.FIFO and RFSTATUS.FIFOP

only apply to the RXFIFO.

The TXFIFO may be flushed by issuing a

SFLUSHTX command strobe. Similarly, a

SFLUSHRX command strobe will flush the

receive FIFO.

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