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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CC2430-RTR1-F64Z датащи(PDF) 211 Page - Texas Instruments |
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CC2430-RTR1-F64Z датащи(HTML) 211 Page - Texas Instruments |
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211 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 211 of 232 Bit Name Reset R/W Description 7:6 LOCK_THR[1:0] 01 R/W Number of consecutive reference clock periods with successful sync windows required to indicate lock: 00 : 64 01 : 128 10 : 256 11 : 512 5 CAL_DONE 0 R Frequency synthesizer calibration done. 0 : Calibration not performed since the last time the FS was turned on. 1 : Calibration performed since the last time the FS was turned on. 4 CAL_RUNNING 0 R Calibration status, '1' when calibration in progress. 3 LOCK_LENGTH 0 R/W LOCK_WINDOW pulse width: 0: 2 CLK_PRE periods 1: 4 CLK_PRE periods 2 LOCK_STATUS 0 R PLL lock status 0 : PLL is not in lock 1 : PLL is in lock 1:0 FREQ[9:8] 01 (2405 MHz) R/W Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. [] [] () [] () MHz 2 0 : 9 2048 MHz 0 : 9 2048 4 0 : 9 2048 RXEN FREQ f FREQ f FREQ division Frequency LO RF ⋅ − + = + = ⇔ + = Table 60: Register FSCTRLH (0xDF10) Bit Name Reset R/W Description 7:0 FREQ[7:0] 0x65 (2405 MHz) R/W Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. [] [] () [] () MHz 2 0 : 9 2048 MHz 0 : 9 2048 4 0 : 9 2048 RXEN FREQ f FREQ f FREQ division Frequency LO RF ⋅ − + = + = ⇔ + = Table 61: Register FSCTRLL (0xDF11) |
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