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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F373VC датащи(PDF) 102 Page - STMicroelectronics |
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STM32F373VC датащи(HTML) 102 Page - STMicroelectronics |
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102 / 137 page  Electrical characteristics STM32F373xx 102/137 DocID022691 Rev 7 Figure 29. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. Offset(3) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) -- - ±10 mV Given for the DAC in 10-bit at VREF+ = 3.6 V -- ±3 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V -- ±12 LSB Gain error(3) Gain error Given for the DAC in 12bit configuration -- ±0.5 % tSETTLING(3) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ -3 4 µs Update rate(3) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ -- 1 MS/s tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. -6.5 10 µs PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement No RLOAD, CLOAD = 50 pF - -67 -40 dB 1. Guaranteed by design. 2. Quiescent mode refers to the state of the DAC keeping a steady value on the output, so no dynamic consumption is involved. 3. Guaranteed by characterization. Table 63. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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