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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32MP157D датащи(PDF) 237 Page - STMicroelectronics |
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STM32MP157D датащи(HTML) 237 Page - STMicroelectronics |
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237 / 261 page  DS12504 Rev 6 237/261 STM32MP157A/D Electrical characteristics 239 6.3.39 DSI PHY characteristics 6.3.40 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 115 and Table 116 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 13: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 0x10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5×VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Table 114. DSI PHY characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCK DSI link clock frequency High-Speed mode (HS) 40 - 500 MHz rate Data rate per lane High-Speed mode (HS) 80 - 1000 Mbps UI Unit interval Equal to 0.5/fCK (HS) 1 - 12.5 ns tclkhs2lp Time to switch DSI_CK from High-Speed to LP Fixed part - - 232 ns Variable part UI = 0.5/fCK (HS) - - 136 UI tclklp2hs Time to switch DSI_CK from LP to High-Speed Fixed part - - 512 ns Variable part UI = 0.5/fCK (HS) -- 40 UI ths2lp Time to switch DSI_Dx from High-Speed to LP Fixed part - - 128 ns Variable part UI = 0.5/fCK (HS) -- 64 UI tlp2hs Time to switch DSI_Dx from LP to High-Speed Fixed part - - 256 ns Variable part UI = 0.5/fCK (HS) -- 32 UI IDDA1V2_DSI_PHY(PHY) Power down Fixed part - 185 - µA High-Speed TX 2 lanes in High-Speed mode - 17.35 - mA LPDT transmit All data lanes in LPDT mode - 3.35 - LPDT receive All data lanes in LPDT mode - 0.8 - IDDA1V8_DSI(PHY) Power down - - 1 - µA High-Speed TX 2 lanes in High-Speed mode - 400 - LPDT transmit All data lanes in LPDT mode - 1 - LPDT receive All data lanes in LPDT mode - 1 - 1. Guaranteed by design unless otherwise specified. |
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