STM32MP153A datasheet(207/256 Pages) STMICROELECTRONICS

номер детали	STM32MP153A

подробное описание детали	Arm® dual Cortex®-A7 800 MHz Cortex®-M4 MPU, TFT, 37 comm. interfaces, 29 timers, adv. analog

PDF	256 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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207 / 256 page

DS12502 Rev 6

207/256

STM32MP153A/D

Electrical characteristics

234

Table 90. DFSDM measured timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM clock

1.71 V < VDD < 3.6 V

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 V < VDD < 3.6 V

(fDFSDMCLK

/4)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < VDD < 3.6 V

(fDFSDMCLK

/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

(fDFSDMCLK

/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

2.7 < VDD < 3.6 V

(fDFSDMCLK

/4)

fCKOUT

Output clock

frequency

1.71 < VDD < 3.6 V

DuCyCKOUT

Output clock

frequency duty

cycle

1.71 < VDD

< 3.6 V

Even division

CKOUTDIV[7:0] = n

1,3,5,..

Odd division

CKOUTDIV[7:0] = n

2,4,6,..

(((n/2+1)/

(n+1))*100)-5

((n/2+1)/

(n+1))*100

(((n/2+1)/

(n+1))*100)

twh(CKIN)

twl(CKIN)

Input clock

high and low

time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

TCKIN/2 - 0.5

TCKIN/2

tsu

Data input

setup time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

Data input hold

time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

0.5

TManchester

Manchester

data period

(recovered

clock period)

Manchester mode (SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0]≠0),

1.71 < VDD < 3.6 V

(CKOUTDIV+

×TDFSDMCLK

(1)

(2×CKOUT

DIV) ×

TDFSDMCLK

(1)

1. See DFSDM section in RM0442 reference manual for definition of CKOUTDIV.

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