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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCIMX6DP5AVT2AB датащи(PDF) 109 Page - NXP Semiconductors |
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PCIMX6DP5AVT2AB датащи(HTML) 109 Page - NXP Semiconductors |
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109 / 166 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 NXP Semiconductors 109 4.12.12.2 D-PHY Signaling Levels The signal levels are different for differential HS mode and single-ended LP mode. Figure 66 shows both the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below the LP low-level input threshold such that LP receiver always detects low on HS signals. Figure 66. D-PHY Signaling Levels LP Line Receiver DC Specifications VIL Input low voltage — — — 550 mV VIH Input high voltage — 920 — — mV VHYST Input hysteresis — 25 — — mV Contention Line Receiver DC Specifications VILF Input low fault threshold — 200 — 450 mV Table 68. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit HS Vout Range HS Vcm Range Max VOD Min VOD VCMTX,MIN VOLHS VCMTX,MAX VOHHS LP VIL LP VOL LP VIH VOH,MAX VOH,MIN VIH VIL LP Threshold Region VGNDSH,MA X VGNDSH,MIN GND LP VOL HS Differential Signaling LP Single-ended Signaling |
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