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AM6548 датащи(PDF) 165 Page - Texas Instruments

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номер детали AM6548
подробное описание детали  AM654x, AM652x Sitara??Processors Silicon Revision 2.1
PDF  282 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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AM6548 датащи(HTML) 165 Page - Texas Instruments

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7.9.5 Peripherals
7.9.5.1 VIN
Table 7-26, Figure 7-30, and Figure 7-31 present timing requirements for LVDSRX interface.
Table 7-25 presents timing conditions for LVDSRX.
Table 7-25. LVDSRX Timing Conditions
PARAMETER
MODE
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
1.8 V
1.3
2.64
V/ns
3.3 V
1.5
2.64
V/ns
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
50
ps
Table 7-26. Timing Requirements for LVDSRX
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
V1
tc(PCLK)
Cycle time, VIN0_PCLK
5.76
(1)
ns
V2
tw(PCLKH)
Pulse duration, VIN0_PCLK high
0.45 × P
(2)
ns
V3
tw(PCLKL)
Pulse duration, VIN0_PCLK low
0.45 × P
(2)
ns
V4
tsu(PCLK-CTL/DATA)
Input setup time, control (VIN0_HD, VIN0_VD) and data
(VIN0_DATA[15:0]) valid to VIN0_PCLK transition
2.42
ns
V5
th(CTL/DAT-PCLK)
Input hold time, VIN0_PCLK transition to control (VIN0_HD,
VIN0_VD) valid
0.52
ns
(1)
For maximum frequency of 165 MHz
(2)
P = VIN0_PCLK period
CAL_CCDC_TIMINGS_01
VIN0_PCLK
V2
V1
V3
Figure 7-30. LVDSRX Input Clock Signal
VIN0_PCLK
(Negative-edge clocking)
VIN_DATA[15:0]
CAL_CCDC_TIMINGS_02
V4
V5
VIN0_PCLK
(Positive-edge clocking)
Figure 7-31. LVDSRX Input Timings
7.9.5.2 CPSW2G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
7.9.5.2.1 CPSW2G MDIO Interface Timings
Table 7-28, Table 7-29, and Figure 7-32 present timing requirements for MDIO.
Table 7-27 presents timing conditions for CPSW2G MDIO.
www.ti.com
AM6548, AM6528, AM6526
SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: AM6548 AM6528 AM6526



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