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STM32H747AI датащи(PDF) 174 Page - STMicroelectronics

номер детали STM32H747AI
подробное описание детали  Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
PDF  252 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32H747AI датащи(HTML) 174 Page - STMicroelectronics

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Electrical characteristics
STM32H747xI/G
164/242
DS12930 Rev 1
Table 86. Synchronous multiplexed PSRAM write timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
2Tfmc_ker_ck –1
1
-
Ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x =0..2)
-
1
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x = 0…2)
Tfmc_ker_ck +0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x =16…25)
-2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x =16…25)
Tfmc_ker_ck
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
-
1.5
t(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck +0.5
-
td(CLKL-ADV)
FMC_CLK low to to FMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK
low
-2.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck +0.5
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
2
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
2
-



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