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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LITE39 датащи(PDF) 149 Page - STMicroelectronics |
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ST7LITE39 датащи(HTML) 149 Page - STMicroelectronics |
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149 / 167 page  ST7LITE3 149/167 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40°C to 85°C, unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 130 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) 1 V VOL Output low level voltage 2) VDD=5V IIO=+5mA TA≤85°C TA≥85°C 0.5 - 1.0 1.2 V IIO=+2mA TA≤85°C TA≥85°C 0.45 - 0.7 0.9 RON Pull-up equivalent resistor 3) 1) VDD=5V TA≤85°C 10 46 70 k Ω VDD=3V 91 k Ω tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time 4) 20 µs tg(RSTL)in Filtered glitch duration 200 ns |
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