AM6546 datasheet(158/277 Pages) TI1

158 / 277 page

158

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

5.9.4.3

PLLs

Power is supplied to the PLL by internal regulators that derive power from the off-chip power-supply.

There are total nine Phase Locked Loops (PLLs) in the device:

•

MCU_PLL0 (MCU PLL) with WKUP_PLL_CTRL0: The MCU PLL — which is used to drive the switch

fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the

various clock divisions, gating, and synchronization in WKUP domain and MCU domain.

•

MCU_PLL1 (CPSW PLL): The MCU_PLL1, which is used to drive the CPSW.

•

PLL0 (MAIN PLL) with PLL_CTRL0: The Main PLL — which is used to drive the switch fabrics,

accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the various

clock divisions, gating, and synchronization in MAIN domain.

•

PLL1 (PER0 PLL): The PER0 PLL, which is used to drive the Peripherals in MAIN Domain.

•

PLL2 (PER1 PLL): The PER1 PLL, which is used to drive the PRU_ICSSG.

•

PLL3 (DDR PLL): The DDR PLL is used to drive the DDR PHY for the DDRSS.

•

PLL4 (DSS PLL): The DSS PLL, which is used to drive the Display Subsystem.

•

PLL6 (ARM0 PLL): The ARM0 PLL, which is used to drive the ARM0.

•

PLL7 (ARM1 PLL): The ARM1 PLL, which is used to drive the ARM1.

Most of the Device is driven by the output from the main PLL except the following items:

•

Arm subsystem has its own dedicated PLL.

•

MCU subsystem has its own dedicated PLL

•

EMIF DDR subsystem has its own dedicated PLL to drive DDR PHY and DDRSS.

•

PRU_ICSSG has clocks sourced from several PLLs:

–

PER0 PLL to generate UART clock,

–

PER1 PLL to generate Core clock,

–

MAIN PLL to generate Industrial Ethernet Peripheral clock,

–

CPSW PLL to generate Ethernet clocks.

•

DSS has its own dedicated PLL, to generate Pixel Clock.

•

PCIESS require separate reference clocks to drive SERDES PHYs.

NOTE

For more information, see:

•

Device Configuration / Clocking / PLLs section of the device TRM

•

Peripherals / Display Subsystem Overview section of the device TRM

•

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -

Gigabit (PRU_ICSSG) section of the device TRM

NOTE

The input reference clock (OSC1_XI/OSC1_XO) are specified and the lock time is ensured

by the PLL controller, as documented in the Device Configuration chapter of the device TRM.

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