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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32MP153A датащи(PDF) 188 Page - STMicroelectronics |
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STM32MP153A датащи(HTML) 188 Page - STMicroelectronics |
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188 / 254 page  Electrical characteristics STM32MP153A/D 188/254 DS12502 Rev 3 6.3.20 QUADSPI interface characteristics Unless otherwise specified, the parameters given in Table 71 and Table 72 for QUADSPI are derived from tests performed under the ambient temperature, Faxiss_ck frequency and VDD supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5×VDD • I/O compensation cell enabled • HSLV activated when VDD ≤ 2.7 V Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics. Table 70. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter Min Max Unit tw(NWE) FMC_NWE low width 4Tfmc_ker_ck-1 4Tfmc_ker_ck+1 ns tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3Tfmc_ker_ck - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 4Tfmc_ker_ck-3 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 2Tfmc_ker_ck+1 th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3Tfmc_ker_ck+0.5 - 1. Guaranteed by characterization results. Table 71. QUADSPI characteristics in SDR mode Symbol Parameter Conditions Min Typ Max Unit Fck1/t(CLK) QUADSPI clock frequency 2.7 V ≤ VDD < 3.6 V CL = 20 pF - - 166 MHz 1.71 V < VDD <3.6 V CL = 15 pF -- 90 tw(CLKH) QUADSPI clock high and low time - t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 ns tw(CLKL) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 ts(IN) Data input setup time - 1.25 - - th(IN) Data input hold time - 2.75 - - tv(OUT) Data output valid time - - 1 1.5 th(OUT) Data output hold time - 0 - - |
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