STM32MP151D datasheet(250/253 Pages) STMICROELECTRONICS

250 / 253 page

Revision history

STM32MP151A/D

250/253

DS12500 Rev 3

Revision history

Table 124. Document revision history

Date

Revision

Changes

08-Feb-2019

Initial release.

01-Aug-2019

Updated ADC characteristics on cover page.

Updated Table 1: STM32MP151A/D features and

peripheral counts

Updated Section 3.7.1: Power supply scheme.

Updated Table 7: STM32MP151A/D pin and ball

definitions.

Updated Table 8: Alternate function AF0 to AF7.

Updated Table 10: Voltage characteristics.

Updated Table 13: General operating conditions.

Updated Table 14: Operating conditions at power-up /

power-down.

Updated Table 15: Embedded reset and power control

block characteristics.

Updated Figure 13: VDDCORE rise time from reset.

Updated Table 15: Embedded reset and power control

block characteristics.

Updated Table 16: Embedded reference voltage.

Updated Table 18: REG1V1 embedded regulator

(USB_PHY) characteristics.

Updated Table 19: REG1V8 embedded regulator (USB)

characteristics.

Updated Table 20: Current consumption (IDDCORE) in

Run mode.

Updated Table 21: Current consumption (IDD) in Run

mode.

Updated Table 22: Current consumption in Stop mode.

Updated Table 23: Current consumption in LPLV-Stop

mode.

Updated Table 25: Current consumption in VBAT mode.

Updated Table 28: High-speed external user clock

characteristics (digital bypass).

Updated Table 29: High-speed external user clock

characteristics (analog bypass).

Added Table 30: Low-speed external user clock

characteristics (analog bypass).

Added Figure 17: Low-speed external clock source AC

timing diagram (analog bypass).

Updated Table 32: 8-48 MHz HSE oscillator

characteristics.

Updated Figure 19: Typical application with a 24 MHz

crystal.

Updated Figure 20: Typical application with a

32.768 kHz crystal.

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