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STM32MP151D датащи(PDF) 222 Page - STMicroelectronics |
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STM32MP151D датащи(HTML) 222 Page - STMicroelectronics |
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222 / 253 page ![]() Electrical characteristics STM32MP151A/D 222/253 DS12500 Rev 3 Table 102. Dynamic characteristics: SD / MMC / e•MMC characteristics, VDD = 2.7 V to 3.6 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 130 MHz - SDIO_CK/fpclk2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 - ns tW(CKH) Clock high time 8.5 9.5 - CMD, D inputs (referenced to CK) in MMC and SD HS/SDR(3)/DDR(3) mode tISU Input setup time HS - 1.5 - - ns tIH Input hold time HS 1.5 - - tIDW(4) Input valid window (variable window) 2.5 - - CMD, D outputs (referenced to CK) in MMC and SD HS/SDR(3)/DDR(3) mode tOV Output valid time HS - -5 6.5 ns tOH Output hold time HS 2.5 - - CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD - 1.5 - - ns tIHD Input hold time SD 1.5 - - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD - -0.5 1.5 ns tOHD Output hold default time SD 0 - - 1. Guaranteed by characterization results. 2. Above 100 MHz, CL = 20 pF. 3. For SD 1.8 V support, an external voltage converter is required. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 103. Dynamic characteristics: SD / MMC / e•MMC characteristics VDD = 1.71 V to 1.9 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 105 MHz - SDIO_CK/fpclk2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 - ns tW(CKH) Clock high time 8.5 9.5 - CMD, D inputs (referenced to CK) in e•MMC mode tISU Input setup time HS - 1.5 - - ns tIH Input hold time HS 2.5 - - tIDW(3) Input valid window (variable window) 3 - - CMD, D outputs (referenced to CK) in e•MMC mode |
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