LPC47M14X datasheet(201/205 Pages) SMSC

номер детали	LPC47M14X

подробное описание детали	128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB

PDF	205 Pages

Scroll/Zoom	100%

производитель	SMSC [SMSC Corporation]

домашняя страница	http://www.smsc.com

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201 / 205 page

SMSC DS – LPC47M14X

Page 201

Rev. 03/19/2001

12 APPENDIX - TEST MODE

12.1 BOARD TEST MODE

Board test mode can be entered as follows:

On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low.

Exit board test mode as follows:

On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high.

See the “XNOR-Chain Test Mode” section below for a description of this board test mode.

12.1.1

XNOR-Chain Test Mode

XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly

and test operations. See FIGURE 49 below.

The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the

LPC47M14x pin functions are disconnected from the device pins, which all become input pins except for one output

pin at the end of XNOR-Chain.

The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware

to control the device pins and observe the results at the XNOR-Chain output pin.

The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is 85, GP31/FAN_TACH.

See the following subsections for more details.

FIGURE 49 – XNOR-CHAIN TEST STRUCTURE

I/O#1

I/O#2

I/O#3

I/O#n

XNor

Out

LPC47M14X датащи(PDF) 201 Page - SMSC Corporation