LPC47M14X datasheet(169/205 Pages) SMSC

169 / 205 page

SMSC DS – LPC47M14X

Page 169

Rev. 03/19/2001

NAME

REG INDEX

DEFINITION

NOTES

INT_G

Default = 0x00

on VCC POR, VTR

POR,

HARD

RESET and SOFT

RESET

0xF1

R/W

Bit[7:1] Reserved

Bit[0]

INT_G Enable

0 = Disable Interrupt Generating Registers

from affecting the serial IRQ stream.

1 = Enable Interrupt Generating Registers to

drive one or more frames low in the

SER IRQ stream

Note:

See

runtime registers at offset 0x54 and

0x55 for configuring Interrupt Generating

Registers.

Eng.

Note 1

0xF2-

0xFF

Reserved – read as ‘0’

Note:

The registers located in Logical Device A are runtime registers.

Note 1: SMSC Reserved registers have read/write capability. The default values set for these registers should be

maintained unless otherwise specified.

Table 74 – MPU-401 [Logical Device Number = 0x0B]

NAME

REG INDEX

DEFINITION

STATE

MPU-401

Primary

Base I/O Address

High Byte

Default = 0x03

on HARD RESET,

SOFT RESET, VCC

POR and VTR POR

0x60 R/W

Bit[0] A8

Bit[1] A9

Bit[2] A10

Bit[3] A11

Bit[4] “0”

Bit[5] “0”

Bit[6] “0”

Bit[7] “0”

MPU-401

Primary

Base I/O Address

Low Byte

Default = 0x30

on HARD RESET,

SOFT RESET, VCC

POR and VTR POR

0x61 R/W

Bit[0] “0”

Bit[1] A1

Bit[2] A2

Bit[3] A3

Bit[4] A4

Bit[5] A5

Bit[6] A6

Bit[7] A7

Note: Bit[0] must be “0”.

Table 75 – USB Hub, Logical Device C [Logical Device Number = 0x0C]

NAME

REG INDEX

DEFINITION

NOTES

Activate

0x30

Bit [0]

This bit has read/write capability.

Bits[7:1] Reserved (Writes are ignored and Reads

return 0)

Note:

This register has no dedicated function. The

user may use this register at their own

discretion.

Note 1

OSC_CLK

Default = 0x00

on VTR POR

0xF0

R/W

Bit [0] Reserved

Bit [1] OSC_CLK

0=48MHz clock is connected to the ICLK pin (default)

1=24MHz crystal is connected to the ICLK and OCLK

pins

Bits [7:2] Reserved

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