LPC47M14X datasheet(130/205 Pages) SMSC

130 / 205 page

SMSC DS – LPC47M14X

Page 130

Rev. 03/19/2001

NAME

REG OFFSET

(hex)

DESCRIPTION

PME_EN1

Default = 0x00

on VTR POR

(R/W)

PME Wake Enable Register 1

This register is used to enable individual LPC47M14x

PME wake sources onto the nIO_PME wake bus.

When the PME Wake Enable register bit for a wake

source is active (“1”), if the source asserts a wake event

so that the associated status bit is “1” and the PME_En

bit is “1”, the source will assert the nIO_PME signal.

When the PME Wake Enable register bit for a wake

source is inactive (“0”), the PME Wake Status register

will indicate the state of the wake source but will not

assert the nIO_PME signal.

Bit[0] Reserved (Note 7)

Bit[1] RI2

Bit[2] RI1

Bit[3] KBD

Bit[4] MOUSE

Bit[5] SPEKEY (Wake on specific key)

Bit[6] FAN_TACH1

Bit[7] FAN_TACH2

The PME Wake Enable register is not affected by Vcc

POR, SOFT RESET or HARD RESET.

PME_EN2

Default = 0x00

on VTR POR

(R/W)

PME Wake Enable Register 2

This register is used to enable individual LPC47M14x

PME wake sources onto the nIO_PME wake bus.

When the PME Wake Enable register bit for a wake

source is active (“1”), if the source asserts a wake event

so that the associated status bit is “1” and the PME_En

bit is “1”, the source will assert the nIO_PME signal.

When the PME Wake Enable register bit for a wake

source is inactive (“0”), the PME Wake Status register

will indicate the state of the wake source but will not

assert the nIO_PME signal.

Bit[0] GP10

Bit[1] GP11

Bit[2] GP12

Bit[3] GP13

Bit[4] GP14

Bit[5] GP15

Bit[6] GP16

Bit[7] GP17

The PME Wake Enable register is not affected by Vcc

POR, SOFT RESET or HARD RESET.

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