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STM32WB55CC датащи(PDF) 145 Page - STMicroelectronics |
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STM32WB55CC датащи(HTML) 145 Page - STMicroelectronics |
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145 / 165 page ![]() DS11929 Rev 3 145/165 STM32WB55xx Electrical characteristics 152 Figure 26. SPI timing diagram - slave mode and CPHA = 0 tsu(MI) Data input setup time Master mode 1.5 - - ns tsu(SI) Slave mode 1 - - th(MI) Data input hold time Master mode 5 - - th(SI) Slave mode 1 - - ta(SO) Data output access time Slave mode 9- 34 tdis(SO) Data output disable time 9 - 16 tv(SO) Data output valid time Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 -14.5 15.5 ns Slave mode 1.65 < VDD < 3.6 V Voltage Range 1 -15.5 24 Slave mode 1.65 < VDD < 3.6 V Voltage Range 2 -19.5 26 tv(MO) Master mode (after enable edge) - 2.5 3 th(SO) Data output hold time Slave mode (after enable edge) 8 - - th(MO) Master mode (after enable edge) 1 - - 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. Table 90. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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