AR8327-AL1A-R datasheet(384/394 Pages) ETC2

384 / 394 page

384 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

384 • June 2011

COMPANY CONFIDENTIAL

4.4 Power-on Strapping

Table 4-4 shows the pin-to-PHY core

configuration signal power-on strapping.

IIH

Input high current

—

–0.4

IIL

Input low current

0.4

—

VIH

Input high voltage

1.7

3.6

VIL

Input high voltage

—

0.7

Table 4-3.

RGMII/GMII DC Characteristics

Table 4-4.

Power-On Strapping

Pin Name

Pin Signal

Description

Mode_oclk_selH

RXD1_0

A69

Controls the voltage output of switching regulator at

LX. 0 for 1.1V

Use external 1.1V power source, the external power

source must be between 1.1V and 1.26V

AZ_EN

RXDV_1

A54

Disable 802.3az

Enable 802.3az

MDIO_EN

SPI_DO

B44

UART interface

MDIO interface

UART_SPEED

RXD0_0

A68

Normal operation

High speed for function test

control_dac[1]

RX_D0_1

A55

power-saving mode — set in concert with pin A70,

below

2’b00: Power-saving off

2’b01: Power-saving mode 1

2’b10: Power-saving mode 2

2’b11: Power-saving mode 3

control_dac[0]

RX_D2_0

A70

power-saving mode — set in concert with pin A55,

above

SPI_SIZE

RXD2_1

B49

4K or 2K

FUNC_MODE0

SPI_CS

A52

Normal Operation

FUNC_MODE1

SPI_CLK

B45

Test Mode

LED_OPEN_EN

INT_n

B68

Driver

Open Drain

SPI_EN

RXCLK_0

A65

No EEPROM connected

EEPROM enable

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