AR8327-AL1A-R datasheet(371/394 Pages) ETC2

371 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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371

3.10.28 Debug Register—Hib Control and

Auto Negotiation Test Register

Address Offset: 0x0B

Table 3-393.

Hib Control and Auto Negotiation Test Register

Bit

Symbol

Type

Description

PS_HIB_EN

Mode

R/W

Power hibernation control bit

1 = hibernation enable

0 = hibernation disable

HW Rst

SW Rst

Retain

WAKE_MODE

Mode

R/W

1 = PHY wakes up by energy detect or wake-up pin

0 = PHY wakes up only by energy detect

HW Rst

SW Rst

Retain

EN_ANY_CHANG

Mode

R/W

1 = Turn on/off analog end at the same time

0 = Turn on/off analog end step by step

HW Rst

SW Rst

Retain

HIB_PULSE_SW

Mode

R/W

1 = PHY sends NLP pulse and detects signal from

cables at hibernation state

0 = PHY does not send NLP pulse but detects signal

from cables at hibernation state

HW Rst

SW Rst

Retain

GATE_25M_EN_S

Mode

R/W

Always 1.

1 = Shut down the 25 MHz clock of auto negotiation

at hibernation state

0 = The 25 MHz clock of auto negotiation is not

controlled by hibernation

HW Rst

SW Rst

SEL_RST_80U

Mode

R/W

Duration of the reset triggered by speed mode change

1 = 80/120/160/240 µs (see bit 9:8 of this register)

0 = 240 µs

HW Rst

SW Rst

Retain

9:8

SEL_RST_TIMER

Mode

R/W

Duration configuration for reset timer

00 = 80 µs

01 = 120 µs

10 = 160 µs

11 = 240 µs

HW Rst

SW Rst

Retain

RESERVED

Mode

Always 0

HW Rst

SW Rst

6:5

GTX_DLY_VAL

Mode

R/W

GTx clock delay select

HW Rst

SW Rst

Retain

BYPASS_BREAK_LI

NK_TIMER

Mode

R/W

1 = BREAL_LINK timer is bypassed when auto

negotiation is restarted, thus auto negotiation state

stays at TRANSMIT_DISABLE for one cycle (40 ns)

0 = Auto negotiation state stays at

TRANSMIT_DISABLE for about 1.2 second when

auto negotiation is restarted

HW Rst

SW Rst

Retain

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