AR8327-AL1A-R datasheet(364/394 Pages) ETC2

364 / 394 page

364 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

364 • June 2011

COMPANY CONFIDENTIAL

3.10.20 Receive Error Counter Register

Address Offset: 0x15, or 0d21

Table 3-385, “Status Register,” on page 365 summarizes the Register

aneg_now_qual

Mode

R/W

A rise of input pin "aneg_now" will set this bit to 1'b2,

and cause PHY to restart auto-negotiation.

Self-clear.

HW Rst

1’b0

SW Rst

Retain

Rev_aneg_qual

Mode

R/W

Make PHY to auto-negotiate in reversed mode. This bit

takes its value from the input pin "rev_aneg" upon

following:

1 HW reset(fall of rst_dsp_i);

2 PHY SW reset;

3 Rise of aneg_now.

HW Rst

1’b0

SW Rst

Update

Giga_dis_qual

Mode

R/W

Make PHY to disable GIGA mode. This bit takes its

value from the input pin "giga_dis" upon following:

1 HW reset(fall of rst_dsp_i);

2 PHY SW reset;

3 Rise of aneg_now.

HW Rst

1’b0

SW Rst

Update

Cfg_pad_en

Mode

RO, LH

The default value is zero; if this bit is set to one, then the

auto negotiation Arbitration FSM will bypass the

LINK_STATUS_CHECK state when the 10 baset/100

baset ready signal is asserted.

HW Rst

SW Rst

Retain

Mr_ltdis

Mode

R/W

The default value is zero; if this bit is set to one, then the

NLP Receive Link Integrity Test FSM will stays at the

NLP_TEST_PASS state.

HW Rst

SW Rst

Update

Smartspeed_en

Mode

R/W

The default value is one; if this bit is set to one and cable

inhibits completion of the training phase, then

After a few failed attempts, the DSP PHY automatically

downgrades the highest ability to the next lower speed:

from 1000 to 100 to 10.

HW Rst

SW Rst

Update

4:2

Smartspeed_retr

y_limit

Mode

R/W

The default value is three; if these bits are set to three,

then the DSP PHY will attempt five times before

downgrading; The number of attempts can be changed

through setting these bits.

HW Rst

011

SW Rst

Update

Bypass_smartspe

ed_timer

Mode

R/W

The default value is zero; if this bit is set to one, the

Smartspeed FSM will bypass the timer used for

stablility.

HW Rst

SW Rst

Update

Reserved

Mode

Reserved. Must be 0.

HW Rst

SW Rst

Bit

Symbol

Type

Description

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