AR8327-AL1A-R datasheet(345/394 Pages) ETC2

345 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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345

Table 3-366.

Control Register

Bit

Symbol

Type

Description

Reset

Mode

R/W

PHY Software Reset. Writing a "1" to

this bit causes the PHY the reset

operation is done , this bit is cleared to

"0" automatically. The reset occurs

immediately.

1= PHY reset

0 =Normal operation

HW Rst

SW Rst

Loopback

Mode

R/W

When loopback is activated, the

transmitter data presented on TXD is

looped back to RXD internally. Link is

broken when loopback is enabled.

1 = Enable Loopback

0 = Disable Loopback

HW Rst

SW Rst

Speed Selection

Mode

R/W

0.6 0.13

1 1 = Reserved

1 0 = 1000 Mb/s

0 1= 100 Mb/s

0 0 = 10 Mb/s

HW Rst

SW Rst

Auto-negotiation

Mode

R/W

1 = Enable Auto-Negotiation Process

0 = Disable Auto-Negotiation Process

HW Rst

SW Rst

Power Down

Mode

R/W

When the port is switched from power

down to normal operation, software

reset and restart Auto-Negotiation are

performed even when bits Reset (0.15)

and Restart Auto-Negotiation (0.9) are

not set by the user.

1 = Power down

0 = Normal operation

HW Rst

SW Rst

Isolate

Mode

R/W

The GMII/MII output pins are tristated

when this bit is set to 1.

The GMII/MII inputs are ignored.

1 = Isolate

0 = Normal operation

HW Rst

SW Rst

Restart Auto-negotiation

Mode

R/W, SC

Auto-Negotiation automatically

restarts after hardware or software

reset regardless of whether or not the

restart bit (0.9) is set.

1 = Restart Auto-Negotiation Process

0 = Normal operation

HW Rst

SW Rst

Duplex Mode

Mode

R/W, SC

1:Full Duplex

0 :Half Duplex

HW Rst

SW Rst

Collision Test

Mode

R/W

Setting this bit to 1 will cause the COL

pin to assert whenever the TX_EN pin

is asserted.

1 = Enable COL signal test

0 = Disable COL signal test

HW Rst

SW Rst

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