AR8327-AL1A-R datasheet(298/394 Pages) ETC2

298 / 394 page

298 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

298 • June 2011

COMPANY CONFIDENTIAL

3.7.144 ACL_RATE_CTRL0_30

Address 0x0AF0

SFT&HW RST

Table 3-295, “ACL_30 Rate Limit Control Register 0,” on page 298 summerizes the

ACL_RATE_CTRL0_30 Register 0

Table 3-295.

ACL_30 Rate Limit Control Register 0

3.7.145 ACL_RATE_CTRL1_30

Address 0x0AF4

SFT&HW RST

R/W

ACL_RATE_UNIT_29

1: Packets/ 0: bytes

R/W

ACL_CF_29

Coupling flag for ingress rate limit

R/W

ACL_CM_29

Color mode for ingress rate limit

19:18

R/W

2'b01

ACL_RATE_TIME_SLOT_29

ACL Ingress rate limit control timer

slot.

2'b00: 100us;

2'b01: 1ms

2'b10: 10ms

2'b11: 100ms

Notes: if port rate limit set to less than

96kbps, don't select 100us as time slot

17:15

R/W

ACL_EBS_29

Excess burst size for ingress rate limit

14:0

R/W

0x7FFF

ACL_EIR_29

Ingress Rate Limit for all priority.

Rate is limited to times of 32kbps.

Default 15'h7FFF is for disable rate

limit for ingress. if these bits are set to

15'h0, no frame should be received in

from this port.

Bit

R/W

Inital

Value

Mnemonic

Description

Bit

R/W

Inital

Value

Mnemonic

Description

31:18

R/O

RESERVED

17:15

R/W

ACL_CBS_30

Commited burst size for ingress rate

limit

14:0

R/W

0x7FFF

ACL_CIR_30

Ingress Rate Limit for all priority.

Rate is limited to times of 32kbps.

Default 15'h7FFF is for disable rate

limit for ingress. if these bits are set to

15'h0, no frame should be received in

from this port.

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