AR8327-AL1A-R datasheet(125/394 Pages) ETC2

125 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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125

3.6.1

ATU_DATA0

Address 0x0600

SFT&HW RST

Table 3-107 summarizes the ATU_DATA0 Register 0

Table 3-107.

ATU DATA 0 Register 0

3.6.2

ATU_DATA1

Address 0x0604

SFT&HW RST

Table 3-108 summarizes the ATU_DATA1 Register 1

Table 3-108.

ATU DATA 1 Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:0

R/W W

ATU_MAC_ADDR0

this is the MAC address bit [31:0]

Bit

R/W

Inital

Value

Mnemonic

Description

R/W W

ATU_HASH_HIGH_ADDR

Mac hash addr max bit use for get next

R/W W

ATU_SA_DROP_EN

Drop packet enable when source

address is in this entry. If this bit is set

to 1'b1, the packet with sa of this entry

will be dropped.

R/W W

ATU_MIRROR_EN

1: indicates packets should be send to

mirror port and destination port.

0: indicates packets should only be

send to destination port.

R/W W

ATU_PRI_OVER_EN

Priority override enable.

1: indicates ATU_PRI can override any

other priority determined by the

frame's data.

R/W W

ATU_SVL_ENTRY

1'b1: SVL learned;

1'b0: IVL learned

26:24

R/W W

ATU_PRI

This priority bits may be used as

frame's priority when PRI_OVER_EN

set to one.

R/W W

ATU_CROSS_PORT_STATE_EN

1'b1, cross port_state enable

22:16

R/W W

ATU_DES_PORT

These bits indicate which ports are

associated with this mac address when

they are set to one. Bit 16 is assigned to

port0, 17 to port1, 18 to port2,etc

15:0

R/W W

ATU_MAC_ADDR1

mac address bit [47:32]

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