PIC18F4520ESLASHMLQTP datasheet(121/390 Pages) MICROCHIP

121 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 119

PIC18F2420/2520/4420/4520

TABLE 10-9:

PORTE I/O SUMMARY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Function

TRIS

Setting

I/O

Type

Description

RE0/RD/AN5

RE0

DIG

LATE<0> data output; not affected by analog input.

PORTE<0> data input; disabled when analog input enabled.

TTL

PSP read enable input (PSP enabled).

AN5

ANA

A/D input channel 5; default input configuration on POR.

RE1/WR/AN6

RE1

DIG

LATE<1> data output; not affected by analog input.

PORTE<1> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN6

ANA

A/D input channel 6; default input configuration on POR.

RE2/CS/AN7

RE2

DIG

LATE<2> data output; not affected by analog input.

PORTE<2> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN7

ANA

A/D input channel 7; default input configuration on POR.

MCLR/VPP/RE3(1)

MCLR

—

External Master Clear input; enabled when MCLRE configuration bit is

set.

VPP

—

ANA

High-voltage detection; used for ICSP™ mode entry detection. Always

available, regardless of pin mode.

RE3

—(2)

PORTE<3> data input; enabled when MCLRE configuration bit is clear.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note

RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin

devices.

RE3 does not have a corresponding TRIS bit to control data direction.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTE

—

—RE3(1,2)

RE2

RE1

RE0

LATE(2)

—

LATE Data Output Register

TRISE

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1:

Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).

RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

PIC18F4520E/MLQTP датащи(PDF) 121 Page - Microchip Technology

PIC18F4520E/MLQTP датащи(HTML) 121 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL