PIC18F4520ESLASHSP datasheet(279/390 Pages) MICROCHIP

279 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 277

PIC18F2420/2520/4420/4520

BNC

Branch if Not Carry

Syntax:

BNC

Operands:

-128

≤ n ≤ 127

Operation:

if CARRY bit is ‘0’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0011

nnnn

Description:

If the CARRY bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

BNC

Jump

Before Instruction

address (HERE)

After Instruction

If CARRY

address (Jump)

If CARRY

address (HERE + 2)

BNN

Branch if Not Negative

Syntax:

BNN

Operands:

-128

≤ n ≤ 127

Operation:

if NEGATIVE bit is ‘0’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0111

nnnn

Description:

If the NEGATIVE bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

BNN

Jump

Before Instruction

address (HERE)

After Instruction

If NEGATIVE

address (Jump)

If NEGATIVE

address (HERE + 2)

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