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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72F521M датащи(PDF) 157 Page - STMicroelectronics |
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ST72F521M датащи(HTML) 157 Page - STMicroelectronics |
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157 / 199 page  ST72521M/R/AR 157/199 OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fCPU, and TA. Notes: 1. Data based on characterization results, not tested in production. 2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the VIT+(LVD) threshold. Figure 78. LVD Startup Behaviour Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset state is released when VDD is approximately between 0.8V and 1.5V. As a consequence, the I/Os may toggle when VDD is within this window. This may be an issue especially for applications where the MCU drives power components. Because Flash write access is impossible within this window, the Flash memory contents will not be cor- rupted. Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) VD level = High in option byte 4.0 1) 4.2 4.5 V VD level = Med. in option byte VD level = Low in option byte Not Applicable VIT-(LVD) Reset generation threshold (VDD fall) VD level = High in option byte 3.8 4.0 4.25 1) VD level = Med. in option byte VD level = Low in option byte Not Applicable Vhys(LVD) LVD voltage threshold hysteresis 1) VIT+(LVD)-VIT-(LVD) 150 200 250 mV VtPOR VDD rise time 1)2) 6 ∝ µs/V tg(VDD) Filtered glitch delay on VDD 1) Not detected by the LVD 40 ns 5V 1.5V VIT+ 0.8V LVD RESET V D D Window t |
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