L9678P datasheet(155/203 Pages) STMICROELECTRONICS

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L9678P, L9678P-S

General purpose output (GPO) drivers

202

Figure 55. GPO driver block diagram - HS configuration

The drivers have to be configured in one of the two modes through the GPO Configuration

allowed during the Init and Diag states.

When configured as high-side, the drivers need ER Boost voltage to be above the

VERBST_OK threshold to be enabled.

The default state of both drivers is off. The drivers can be independently activated via SPI

control bits on GPO Control Register (GPOCTRLx). In addition, a set point on the

GPOCTRLx will control the output drivers in PWM with a 125Hz frequency. If PWM control is

desired, user should set the needed set point in the GPOxPWM bits of the GPOCTRLx

while activating the interface. When all bits are set to '0', the GPOx output will be disabled.

PWM control is based on a 125 Hz frequency. 6 bits of GPOCTRLx are reserved to this

mode, in order to control the drivers with 64 total levels from a 0% to a full 100% duty cycle.



When both GPO channels are used in PWM Mode at the same frequency they are

synchronized to provide parallel configuration capability.

PWM control is implemented through a careful slew rate control to mitigate EMC emissions

while operating the interface. The driver output structure is designed to stand -1V on its

terminals and a +1V reverse voltage across source and drain.

The GPO driver is protected against short circuits and thermal overload conditions. The

output driver contains diagnostics available in the GPO Fault Status Register (GPOFLTSR).

All faults except for thermal overload will be latched until the GPOFLTSR register is read.

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