AT89C5131A-RDTIM datasheet(125/184 Pages) ATMEL

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125

AT89C5130A/31A-M

4337C–USB–02/05

Bulk/Interrupt IN Transactions

in Standard Mode

Figure 61. Bulk/Interrupt IN Transactions in Standard Mode

An endpoint will be first enabled and configured before being able to send Bulk or Inter-

rupt packets.

The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-

STAX register to allow the USB controller to send the data stored in FIFO at the next IN

request concerning this endpoint. To send a Zero Length Packet, the firmware will set

the TXRDY bit without writing any data into the endpoint FIFO.

Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK

handshake for each IN requests.

To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The

packet stored in the endpoint FIFO is then cleared and a new packet can be written and

sent.

When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in

the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO with

new data.

The firmware will never write more bytes than supported by the endpoint FIFO.

All USB retry mechanisms are automatically managed by the USB controller.

DATA0 (n Bytes)

ACK

HOST

UFI

C51

Endpoint FIFO Write Byte 1

NAK

TXCMPL

Endpoint FIFO Write Byte 2

Endpoint FIFO Write Byte n

Set TXRDY

Clear TXCMPL

Endpoint FIFO Write Byte 1

AT89C5131A-RDTIM датащи(PDF) 125 Page - ATMEL Corporation