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  • Part No.CDC536
    ManufacturerTI2
    Size350 Kbytes
    Pages16 pages
    Description3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
    Datasheet Summary with AI

    # CDC536 3.3-V Phase-Lock Loop Clock Driver

    ## Features
    ️· Low-Output Skew for Clock Distribution and Generation
    ️· Operates at 3.3-V VCC
    ️· Distributes One Clock Input to Six Outputs
    ️· Select Input Configures Outputs for Variable Frequency
    ️· No External RC Network Required
    ️· Synchronizes Outputs to Clock Input via Feedback Pin (FBIN)
    ️· Applications: Synchronous DRAM, High-Speed Microprocessors
    ️· TTL-Compatible Inputs and Outputs
    ️· Drives 50-Ω Parallel-Terminated Transmission Lines
    ️· Low Power Dissipation via EPIC-II B BiCMOS Design
    ️· Reduces Switching Noise with Distributed VCC and Ground Pins
    ️· Packaged in Plastic 28-Pin Shrink Small Outline Package (SSOP)

    ## Description
    The CDC536 is a high-performance, low-skew, low-jitter clock driver that utilizes a phase-lock loop (PLL) to align clock output signals with the input clock (CLKIN). It’s designed for synchronous DRAMs and microprocessors operating from 50 MHz to 100 MHz (or down to 25 MHz with half-frequency outputs). The feedback input (FBIN) synchronizes output clocks to the input.

    ## Functional Details
    ️· PLL Operation: Precisely aligns clock outputs to the input frequency and phase.
    ️· Output Configuration: Select (SEL) input configures outputs to operate at half or double the input frequency.
    ️· Feedback Input (FBIN): Required for PLL synchronization; connected to one of the six output clocks.
    ️· Output Enable (OE): Controls output state (active or high-impedance).
    ️· Test Input (TEST): Used for factory testing; bypasses PLL.

    ## Electrical Characteristics
    ️· Supply Voltage (VCC): 3 - 3.6 V
    ️· Input High Voltage (VIH): 2 V
    ️· Input Low Voltage (VIL): 0.8 V

    ## Package Options
    ️· Package Type: SSOP (Shrink Small Outline Package)
    ️· Pins: 28

    ## Tape and Reel Information
    ️· SPQ (Standard Pack Quantity): 2000
    ️· Reel Diameter: 330.0 mm
    ️· Reel Width: 16.4 mm
    ️· A0 (Cavity Length): 8.1 mm
    ️· B0 (Cavity Width): 10.4 mm
    ️· P1 (Pitch): 12.0 mm
    ️· W (Tape Width): 16.0 mm
    ️· Pin 1 Quadrant: Q1

    ## Package Dimensions
    ️· Length: 350.0 mm
    ️· Width: 350.0 mm
    ️· Height: 43.0 mm

    # CDC536 3.3-V Phase-Lock Loop Clock Driver

    ## Features
    ️· Low-Output Skew for Clock Distribution and Generation
    ️· Operates at 3.3-V VCC
    ️· Distributes One Clock Input to Six Outputs
    ️· Select Input Configures Outputs for Variable Frequency
    ️· No External RC Network Required
    ️· Synchronizes Outputs to Clock Input via Feedback Pin (FBIN)
    ️· Applications: Synchronous DRAM, High-Speed Microprocessors
    ️· TTL-Compatible Inputs and Outputs
    ️· Drives 50-Ω Parallel-Terminated Transmission Lines
    ️· Low Power Dissipation via EPIC-II B BiCMOS Design
    ️· Reduces Switching Noise with Distributed VCC and Ground Pins
    ️· Packaged in Plastic 28-Pin Shrink Small Outline Package (SSOP)

    ## Description
    The CDC536 is a high-performance, low-skew, low-jitter clock driver that utilizes a phase-lock loop (PLL) to align clock output signals with the input clock (CLKIN). It’s designed for synchronous DRAMs and microprocessors operating from 50 MHz to 100 MHz (or down to 25 MHz with half-frequency outputs). The feedback input (FBIN) synchronizes output clocks to the input.

    ## Functional Details
    ️· PLL Operation: Precisely aligns clock outputs to the input frequency and phase.
    ️· Output Configuration: Select (SEL) input configures outputs to operate at half or double the input frequency.
    ️· Feedback Input (FBIN): Required for PLL synchronization; connected to one of the six output clocks.
    ️· Output Enable (OE): Controls output state (active or high-impedance).
    ️· Test Input (TEST): Used for factory testing; bypasses PLL.

    ## Electrical Characteristics
    ️· Supply Voltage (VCC): 3 - 3.6 V
    ️· Input High Voltage (VIH): 2 V
    ️· Input Low Voltage (VIL): 0.8 V

    ## Package Options
    ️· Package Type: SSOP (Shrink Small Outline Package)
    ️· Pins: 28

    ## Tape and Reel Information
    ️· SPQ (Standard Pack Quantity): 2000
    ️· Reel Diameter: 330.0 mm
    ️· Reel Width: 16.4 mm
    ️· A0 (Cavity Length): 8.1 mm
    ️· B0 (Cavity Width): 10.4 mm
    ️· P1 (Pitch): 12.0 mm
    ️· W (Tape Width): 16.0 mm
    ️· Pin 1 Quadrant: Q1

    ## Package Dimensions
    ️· Length: 350.0 mm
    ️· Width: 350.0 mm
    ️· Height: 43.0 mm

    Part No.CDC536
    ManufacturerTI2
    Size350 Kbytes
    Pages16 pages
    Description3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
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