1. Device Overview:

️· Type: Uniform Sector Flash Memory
️· QE Bit: Default value is 1, permanently enabling Quad operation (IO2 and IO3 pins are active). This *cannot* be changed.

2. Status Registers (Key Bits & Functionality):

️· WIP (Write In Progress):
- Indicates if the device is busy with a write, erase, or status register operation.
- `1`: Busy.
- `0`: Idle.
️· WEL (Write Enable Latch):
- Controls write permissions.
- `1`: Enabled (write commands accepted).
- `0`: Disabled (write commands rejected).
️· TB (Top/Bottom Protect): Non-volatile (OTP)
- Configures the Block Protect area. Affects where Block Protection applies (top or bottom of memory).
- `0`: Top area protection.
- `1`: Bottom area protection.
️· BP0-BP3 (Block Protect Bits): Non-volatile.
- Define the size of software-protected areas.
- `1`: Area is protected from Page Program, Sector Erase, and Block Erase commands.
️· SRP0 & SRP1 (Status Register Protect Bits): Non-volatile. Control how the Status Register itself can be written:
- 0,0: Software Protected - Can be written after a Write Enable.
- 1,0: Power Supply Lock-Down - Protected until next power cycle.
- 1,1: One-Time Programmable (OTP) - Permanently protected. (Special order only).
️· LB1-LB3 (Security Register Lock Bits): OTP. Used to control access to Security Registers. Default state is unlocked (0). Setting to 1 permanently locks the Security Registers.
️· SUS1 & SUS2 (Suspend Bits): Volatile, read only. Indicate if Erase or Program operations are suspended.
️· PE & EE (Error bits): Volatile, read only. Indicate errors during program/erase operations.

3. Block Protection Configuration (with TB):

The `TB` bit and `BP0-BP3` bits together determine the specific memory blocks that are protected. Refer to the table in the original document (Table 30 or similar) for the complete mapping. Each combination defines a protected block of memory.

4. Key Notes & Limitations:

️· QE Bit Permanence: The Quad Enable (QE) bit is permanently set to 1, enabling Quad mode and fixing the IO2 and IO3 pin functionality.
️· SRP1 & SRP0 Special Order: The One-Time Programmable (OTP) status register protection (SRP1=1, SRP0=1) requires a special order.
️· OTP Usage: LB3, LB2 and LB1 bits are One Time Programmable, meaning their values can be set only once.